Shift register having low power mode

ABSTRACT

The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

BACKGROUND

In digital circuit, flip-flop (FF) is known to store one-bit ofinformation. A shift register includes a cascade of flip-flops, whichare used to hold binary data. That is, an ‘N’ bit shift registercontains ‘N’ flip-flops. The shift register is capable of shifting bitseither towards right hand side or towards left hand side. The shiftregister are often found in calculators, computers, and data-processingsystems for performing computations. For example, in neural networkapplications, shift registers are commonly used to accumulate theproduct-sum results. The conventional practice is un-gated shiftregisters, for which all the bits are active regardless of the valuestored. However, in a case where the number of bits of the product-sumresult is less than the total number of bits of the shift register, theunused flip-flops in the shift register would still consume energy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is diagram illustrating a shift register according to someembodiments of the disclosure.

FIG. 2 is a diagram illustrating a shift register according to someembodiments of the disclosure.

FIG. 3 is a diagram illustrating a gating circuit according to someembodiments of the disclosure.

FIG. 4 is a diagram illustrating a shift register according to someembodiments of the disclosure.

FIG. 5 is a diagram illustrating a gating circuit according to someembodiments of the disclosure.

FIG. 6 is a flow diagram illustrating a method for a shift register toenter a low power mode according to some embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are merely examples andare not intended to be limiting. In addition, the present disclosurerepeats reference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and, unlessindicated otherwise, does not in itself dictate a relationship betweenthe various embodiments and/or configurations.

As described above, shift register is configured to hold data and usedfor computation. In a case where the width of data under the computationonly requires flip-flops (FFs) corresponding to the lower bits in theshift register, the FFs corresponding to the upper bits are stillactive. The FFs corresponding to the unused upper bits still consumeenergy. The disclosure introduces a shift register that is capable ofdisabling the FFs corresponding to the unused upper bits according tothe data being input to the shift register. That is, the shift registerof the embodiments is configured to enter a low power mode by disablinga portion of the FFs that are not being used based on the input datathat is currently stored in the FFs of the shift register. The outputdata of the FFs represents the input data that is currently being storedin the FFs, which is utilized to determine whether to disable theportion of the FFs for the subsequent cycle. Detail of the shiftregister would be described below in details.

FIG. 1 is diagram illustrating a shift register 100 according to someembodiments of the disclosure. The shift register 100 includes a firstFF 110, a second FF 120, a gating circuit 140, a clock gating circuit150, and a power gating circuit 160. The first FF 110 and the second FF120 are daisy chained together in series and respectively receive afirst portion of input data Din and a second portion of the input dataDin. In the embodiments, the shift register 100 may be N-bit wide shiftregister that is capable of holding N bits of binary data, where N is aninteger greater than 1. The first portion of the input data Din may bebit 0 thru bit p, i.e., Din [0:p], which may also be referred to aslower bits of the input data. The second portion of the input data Dinmay be bit (p+1) thru bit (N−1), i.e., Din [(p+1):(N−1)], which may bereferred to as upper bits of the input data, where the variable p is aninteger greater than 0. For example, the variable p may be configured tobe 12 in a 20-bit wide shift register. The first portion of the inputdata may be lower twelve bits of the input data Din, i.e., bit 0 thrubit 12, Din[0:11]. The second portion of the input data may be upper 8bits of the input data Din, i.e., bit 12 through bit 19, Din[13:19]. Theexample of 20-bit shift register is used in the specification for thepurpose of illustration only. However, the embodiments are not intendedto limit the width of the shift register and the variable p. In someother embodiments, the width of the shift register (i.e., N) may be 2,4, 8, 16, 20, 32, and so on. The variable p may be configured to be anybit position of N-bit shift registers based on the design requirements.

The first FF 110 includes an input terminal D1, a clock terminal CLK1, areset terminal RST1, an output terminal Q1, and a power terminal PW1.The input terminal D1 is coupled to the first portion of the input dataDin[0:p]. The clock terminal CLK1 is coupled to a clock signal SCLK. Thereset terminal RST1 is coupled to a reset signal SRST. The powerterminal PW1 is coupled to a supply voltage Vs. The output terminal Q1is coupled to the second FF 120 and outputs an output data of the firstFF (e.g., Q[0:p]). The first FF 110 is configured to transit between twostable states. The first FF 110 is configured to change state based onthe received input data Din at the input terminal D1. The state of thefirst FF 110 is reset based on the reset signal RST received at thereset terminal RST1. The state transitions may be synchronous with theclock signal SCLK received at the clock terminal CLK1. However, theembodiments are not intended to limit the disclosure. In some otherembodiments, the first FF 110 may be asynchronous. The state of thefirst FF 110 is represented by the output data at the output terminalQ1. In the embodiments, the output terminal Q1 includes a first outputterminal (e.g., Q1) and a second output terminal (e.g., Q1′) whichoutputs data that is complementary to output data at the first outputterminal.

The second FF 120 includes an input terminal D2, a clock terminal CLK2,a reset terminal RST2, an output terminal Q2, and a power terminal PW2.The input terminal D2 is coupled to the second portion of the input dataDin[(p+1):(N−1)]. The clock terminal CLK2 is coupled to the clock signalSCLK. The reset terminal RST2 is coupled to the reset signal SRST. Thepower terminal PW2 is coupled to the supply voltage Vs. The outputterminal Q2 outputs an output data Q[(p+1):(N−1)]. The second FF 120 isconfigured to transit between two stable states. The second FF 120 isconfigured to change state based on the received input data Din at theinput terminal D2. The state of the second FF 120 is reset based on thereset signal RST received at the reset terminal RST2. The statetransitions may be synchronous with the signal received at the clockterminal CLK2. However, the embodiments are not intended to limit thedisclosure. In some other embodiments, the second FF 120 may beasynchronous. The state of the second FF 120 is represented by theoutput data at the output terminal Q2. In the embodiments, the outputterminal Q2 includes a first output terminal (e.g., Q2) and a secondoutput terminal (e.g., Q2′) which outputs data that is complementary tooutput data at the first output terminal.

The gating circuit 140 includes a first input terminal, a second inputterminal, and an output terminal. The first input terminal receives theoutput data Q[p] from the first FF 110. The second input terminal isconfigured to receive the reset signal SRST. The gating circuit 140 isconfigured to output a gating enable signal SGEn according to the outputdata Q[p] and the clock signal SCLK. In some embodiments, the gatingenable signal SGEn is also coupled to the reset terminal of the secondFF 120 and configured to reset the second FF 120. The operation of thegating circuit 140 would be described later.

The clock gating circuit 150 includes a first input terminal coupled tothe clock signal SCLK, a second input terminal coupled to the outputterminal of the gating circuit 140 for receiving the gating enablesignal SGEn, and an output terminal is coupled to the clock terminalCLK2 of the second FF 120. In the embodiments, the clock gating circuit150 is configured to disable the second FF 120 by clock gatingtechnique. In other words, the output data of the first FF 110 maytrigger a condition for disabling the operation of the second FF 120 bydecoupling the second FF 120 from the clock signal through the gatingcircuit 140. In some embodiments, the clock gating circuit 150 includesa NOR gate (not shown). The NOR gate is configured to receive the clocksignal SCLK at a first input terminal and the gating enable signal SGEnat a second input terminal. According to the gating enable signal SGEn,the NOR gate outputs the clock gating signal SCG. That is, the clocksignal received at the first input terminal may be blocked according tothe gating enable signal SGEn received at the second input terminal. Insome other embodiments, the clock gating circuit 150 may furtherincludes a logic inverter (not shown) coupled at the output terminal ofthe NOR gate according to the designed requirement.

In an embodiment where the second FF 120 is synchronous with a signalreceived at the clock terminal of the second FF120, the second FF 120 isclock gated based on a clock gating signal SCG generated by the clockgating circuit 150. The clock terminal of the second FF 120 is coupledto the output terminal of the clock gating circuit 150 to receive theclock gating signal SGC. Based on the gating enable signal SGEn outputby the gating circuit 140, the clock gating circuit 150 couples eitherthe clock signal SCLK or the clock gating signal SCG to the clockterminal of the clock terminal CLK2 of the second FF 120. In theclocking gating technique of the embodiment, the clock gating signal SCGdoes not transition between states. The state of the second FF 120 wouldnot be changed regardless of the input data received at the inputterminal D2, since the clock gating signal SCG does not transitionbetween states in response to the gating enable signal generated basedon the output data of the first FF 110. As a result, the energy may beconserved since the second FF 120 used for upper bits is disabledthrough the clock gating technique.

The power gating circuit 160 includes a first terminal coupled to thesupply voltage Vs, a second terminal coupled to the power terminal PW2of the second FF 120, and a control terminal coupled to the output ofthe gating circuit 140 for receiving the gating enable signal SGEn. Thepower gating circuit 160 is coupled between the supply voltage Vs andthe second FF 120 and configured to couple or decouple the supplyvoltage Vs to or from the second FF 120 according to the gating enablesignal SGEn output by the gating circuit 140. In other words, the outputdata of the first FF 110 may trigger a condition for disabling theoperation of the second FF 120 through the power gating circuit 160. Inthe embodiments, the power gating circuit 160 is configured to disablethe second FF 120 by decoupling the second FF 120 from the supplyvoltage Vs, which may be referred to as power gating technique. As aresult, the energy may be conserved since the second FF 120 used forupper bit(s) is disabled through the clock gating technique. The powergating circuit 160 may include a p-type transistor as illustrated inFIG. 1 . However, the disclosure is not intended to limited thereto. Inother embodiments, other type of switch, n-type transistor, or any othertype of logic circuit having a switching function may be used forimplementing the power gating circuit 160.

In the embodiments, the shift register 100 may be N-bit shift registersconfigured to handle N bits of input data. FIG. 1 is simplified for thepurpose of illustration. It should be noted that the first FF 110includes a plurality of first FFs 110. Each of first FFs 110 isconfigured to handle one bit of input data within the first portion ofthe input data Din[0:p], respectively. The second FF 120 includes aplurality of second FFs 120. Each of the second FFs 120 is configured tohandle one bit of input data within the second portion of the input dataDin [(p+1):(N−1)], respectively. The total number of the FFs in thefirst and second FFs 110, 120 would be N or greater according to designrequirement.

FIG. 2 is a diagram illustrating a shift register 200 according to someembodiments of the disclosure. The shift register 200 includes a firstFF 210, a second FF 220, a third FF 230, a gating circuit 240, a clockgating circuit 150, and a power gating circuit 160. The first FF 210,the third FF 230, and the second FF 220 are daisy chained together inseries and respectively receive different portions of the input dataDin. In the embodiments, the shift register 200 receives N bits of inputdata Din[0:(N−1)]. The first FF 210 includes a plurality of first FFs210 that respectively receive a first portion of the input data,Din[0:(p−1)]. The second FF 220 includes a plurality of second FFs 220that respectively receives a second portion of the input dataDin[(p+1):(N−1)]. The third FF 230 is coupled between the first andsecond FFs 210, 220 and configured to receive a third portion of theinput data Din[p]. In the embodiment, the variable p may be any integergreater than 1 and less than N−2. In other words, the third portion ofthe input data Din[p] has a bit position that is between the first andsecond portion of the input data. In the embodiments, the input data Dinand output data Q of the first FFs are described collectively as thefirst FF 210 unless specified. Similarly, the input data Din and outputdata Q of the second FFs are described collectively as the second FF 230unless specified.

The first FF 210 includes an input terminal D1, a clock terminal CLK1, areset terminal RST1, an output terminal Q1, and a power terminal PW1.The input terminal D1 is coupled to the first portion of the input dataDin[0:(p−1)]. The clock terminal CLK1 is coupled to a clock signal SCLK.The reset terminal RST1 is coupled to a reset signal SRST. The powerterminal PW1 is coupled to a supply voltage Vs. The output terminal Q1is coupled to the third FF 230 and outputs an output data of the firstFF (e.g., Q[0:p]). The functionality of the first FF 210 is similar tothe first FF 110 as illustrated in the embodiments of FIG. 1 , and thusthe detail description would be omitted here for brevity.

The third FF 230 includes an input terminal D3, a clock terminal CLK3, areset terminal RST3, an output terminal Q3, and a power terminal PW3.The clock terminal CLK3 is coupled to the clock signal SCLK. The resetterminal RST3 is coupled to the reset signal SRST. The power terminalPW3 is coupled to the supply voltage Vs. The input terminal D3 iscoupled to the p-th bit of the input data Din[p] and the output terminalof the first FF 210 (e.g., output terminal of the (p−1)th first FF210[(p−1)]). The output terminal Q3 is coupled to the subsequent secondFF 220 and outputs an output data Q[p]. Similar to the first FF 210, thethird FF 230 is configured to transition between two different statesbased on the input data Din[p], the clock signal SCLK, and the resetsignal SRST. In the embodiments, the output terminal Q3 of the third FF230 is also coupled to an input terminal of the gating circuit 140,which would be described in detail later.

The second FF 220 includes an input terminal D2, a clock terminal CLK2,a reset terminal RST2, an output terminal Q2, and a power terminal PW2.The input terminal D2 is coupled to the second portion of the input dataDin[(p+1):(N−1)]. The clock terminal CLK2 is coupled to the clock signalSCLK. The reset terminal RST2 is coupled to the reset signal SRST. Thepower terminal PW2 is coupled to the supply voltage Vs. The outputterminal Q2 outputs an output data Q[(p+1):(N−1)]. The functionality ofthe first FF 210 is similar to the second FF 120 as illustrated in theembodiments of FIG. 1 , and thus the detail description would be omittedhere for brevity.

In the embodiments, the output data Q[p] corresponding to the p-th bitDin[p] of the input data is coupled to the third FF 230. The output dataQ[p] may be referred to as a threshold bit which may be used as acriterion for disabling the second FF 220. The output data Q[p]generated by the third FF 230 is also coupled to the gating circuit 140.The gating circuit 140 determines whether to disable the second FF 220based on the output data Q[p] corresponding to the third portion of theinput data Din[p]. The state of the output data Q[p] output by the thirdFF 110 may reflect that the number of bits that would be involved in acomputation to be performed to a batch of input data. The batch of inputdata refers to a plurality of input data to be processed in a sequence.For example, the output data bit Q[p] of the third FF 230 is outputbased on initial input data of a batch of data to be processed.Therefore, the width of input data within batch of input data to beprocessed may be assumed to be the same until the process designated forthe batch is completed. Example of the process may be image recognitionin the image processing or any process that processes massive amount ofdata with shift register. For example, each of the images may be dividedinto many different regions in pixels for convolution computation.

In the embodiments, the shift register may be a 20-bit shift register(i.e., N=20), and the variable p may be 11 which signifies 12^(th) bit(i.e., bit 11) of the input data Din. In other words, the second FF 220may be disabled based on the bit 11 of the input data Din[11] which maybe reflected by the output data Q[11] of the third FF 230. The bit 11 isused as a threshold bit for determining whether the computation of thebatch of input data would exceeds 12 bits or not. If not, the FFscorresponding to the upper bits (bit 12-19) of the input data Din may besafely disabled. The gate circuit 140 disables the second FF 220 thathandle the upper bits of the input data Din [11:19]. For example, thegating circuit 140 may detect toggling of the output data Q[1] (anexample of Q[p]) from the third FF 230. The toggling of the output dataQ[1] indicates that the third FF 230 of the shift register 230 is beingused for computation, and therefore, the second FF 220 for handling thesecond portion of the input data Din[(p+1):(N−1)] may not be safelydisabled. On other hand, if the output data Q[p] from the third FF 230does not toggle, the second FF 220 for handling the second portion ofthe input data Din[(p+1):(N−1)] may be safely disabled to conserveenergy. That is, the shift register 200 may enter a low power mode bydisabling the second FF 220.

In detail, the gating circuit 140 generates the gating enable signalSGEn which is coupled to the clock gating circuit 150 and the powergating circuit 160. Based on the gating enable signal SGEn, the clockgating circuit 150 may gate the clock signal SCLK from the clockterminal CLK2 of the second FF 220 as to disable the second FF 220.Furthermore, the power gating circuit 160 may gate the supply voltage Vsfrom the power terminal PW2 of the second FF 220 as to disable thesecond FF 220. In the disclosure, the second FF 220 may be disabledthrough either the clock gating circuit 150, the power gating circuit160, or both.

FIG. 3 is a circuit diagram illustrating a gating circuit 340 accordingto some embodiments of the disclosure. The gating circuit 140 asillustrated in FIGS. 1 and 2 may be implemented by the gating circuit340. With reference to FIG. 3 , the gating circuit 340 includes a latch341, a logic inverter 343, and a FF 345 (may also referred to as agating FF). In the embodiments, the latch 341 includes two cross-coupledNOR gates 3411, 3413.

Input terminal of one of the cross-coupled NOR gate 3411 is coupled tothe output terminal of the third FF 230 in FIG. 2 or the output terminalof the first FF 110. Input terminal of another one of the cross-coupledNOR gate 3413 is coupled to the reset signal SRST. The output terminalof the latch 341 is configured to change states based on the output dataQ[p] and the reset signal SRST.

The FF 345 includes an input terminal D4, a clock terminal CLK4, a resetterminal RST4, a power terminal PW4, a first output terminal Q4, and asecond output terminal Q4 b. The input terminal D4 is coupled to theoutput terminal of the latch 341. The clock terminal CLK4 is coupled tothe clock signal SCLK. The reset terminal RST4 is coupled to the resetsignal SRST. The power terminal PW4 is coupled to a supply voltage Vs.The first output terminal Q4 is configured to output a signal accordingto the input received at the input terminal D4, which may be referred toas a clock gating signal SGEn_gc. Signal output from the second outputterminal Q4 b is complementary of the signal output from the firstoutput terminal Q4 b, which may be referred to as a power gating signalSGEn_gp. In the embodiments, the clock gating signal SGEn_gc is coupledto the clock gating circuit 150 and the reset terminal RST2 of thesecond FF 220. The power gating signal SGEn_gp is coupled to the powergating circuit 160. In some other embodiments, the power gating signalSGEn_gp may be generated by a logic inverter (not shown) by using theclock gating enable signal SGEn_gc, since the power gating signalSGEn_gp and the clock gating enable signal SGEn_gc are complementarysignals. In the disclosure, the clock gating enable signal SGEn_gc andthe power gating enable signal SGEn_gp are collectively described as thegating enable signal SGEn for the purpose of brevity. It should becomprehensive to those skilled in the art that the gating enable signalare used to toggle the operation(s) of the clock gating circuit 150and/or the power gating circuit 160. In the embodiments, the inverter343 is coupled between the output of the latch 341 and the inputterminal D4 of the FF 345.

FIG. 4 is a diagram illustrating a shift register 400 according to someembodiments of the disclosure. Similar to the shift register 200illustrated in FIG. 2 , the shift register 400 includes a first FF 410,the second FF 220, a third FF 430, a gating circuit 240, a clock gatingcircuit 150, and a power gating circuit 160. As compared to the shiftregisters 200 illustrated in FIG. 2 , the third FF 430 includes aplurality of FFs and a first portion of the input data is bit 0 thru bit(p−2) (i.e., Din[0:(p−2)]. The operations of other components in theshift register 400 are similar to the shift register 200 as describedabove unless specified. Instead of depending on one bit of the inputdata Din (e.g., Din[p]), the shift register 400 disables the second FFs220 based on a plurality of bits in the input data Din. In theembodiments, the first FF 410 is configured to receive and handle thefirst portion of the input data Din[0:(p−2)], and the third FF 430 isconfigured to receive and handle a third portion of the input dataDin[(p−1):p]. However, the embodiment is not limited thereto. In otherembodiments, the third register 430 may be configured to receive andhandle more than two bits in the input data Din.

With reference to FIG. 4 , the gating circuit 340 is further coupled toa NOR gate 447 at the first terminal. The NOR gate 447 is configured toreceive the output data Q[(p−1)], Q[p] from the third FF 430 andtransition between states accordingly. Output terminal of the NOR gate447 is coupled to the first terminal of the latch 341. The gatingcircuit 340 generates the gating enable signal SGEn according to theinput data Din[(p−1):p] which is reflected by the output data Q[(p−1):p]from the third FFs 430. The embodiments are not intended to limit thenumber of bits that are utilized for determining whether to disable thesecond FF 220. In some other embodiments, the disablement of the secondFF 220 may be based on 3 or more bits in the input data Din.

In the embodiments described above, the disablement of the second FF 220is based on the third portion of the input data Din, where the thirdportion of the input data Din is between the first and second portion ofthe input data. The output data of the third FF is coupled to the gatingcircuit for activating the disablement of the second FF 220. In someother embodiments, the third portion of the input data Din may be anybit positions in the input data, and the bit positions does not have tobe subsequent to each other. For example, in an example of 20-bit inputdata Din[0:19], the third portion of the input data may be bit 4 Din[4],bit 10 Din[10], bit 15 Din[15], etc. In such embodiments, the shiftregister would include a plurality of third FFs respectively within aplurality of FFs arranged in a sequence. That is, the FF for handlingthe input data Din[4], the FF for handling the input data Din[10], andthe FF for handling the input data Din[15] may be configured as thethird FF as described in the embodiments illustrated in FIGS. 2 and 4 ,which are respectively coupled to the gating circuit. In someembodiments, any one of these input data Din[4], Din[10], Din[15] maytrigger a low power mode by disabling the subsequent FFs in the shiftregister. For example, if Din[4] triggers the low power mode, the gatingcircuit may be configured to disable all of the FFs (i.e., second FF)subsequent to the FF (i.e., third FF) that receives the input dataDin[4]. If Din[10] triggers the low power mode, the gating circuit maybe configured to disable all of the FFs (i.e., second FF) subsequent tothe FF (i.e., third FF) that receives the input data Din[10]. IfDin[15]triggers the low power mode, the gating circuit may be configuredto disable all of the FFs (i.e., second FF) subsequent to the FF (i.e.,third FF) that receives the input data Din[15]. As such, the shiftregister may disable different number of the FFs according to thecomputation required by the input data. In some embodiments, the gatingcircuit and the clock gating circuit may each further include aselection circuit that outputs the gating enable signal SGEn forselectively disable different number of second FFs based on the inputdata Din[5], Din[10], Din[15].

FIG. 5 is a diagram illustrating a gating circuit 540 according to someembodiments of the disclosure. The gating circuit 540 includes acomparator 542 and an FF 545. In the embodiments, the FF 545 has similarfunction and structure as the gating FF 345 illustrated in FIG. 3 . Thecomparator 542 is coupled to the output data Q[0:(N−1)] of the shiftregister and configured to compare the output data Q[0:(N−1)] to apredetermined threshold THR[0:(N−1)]. The output data Q[0:(N−1)] is theexisting data stored in the shift register, and the thresholdTHR[0:(N−1)] may be predefined according to the design requirements. Thecomparator 542 outputs a comparison result to the FF 545, where the FF545 generates and output the gating enable signal SGEn according to thecomparison result. For example, if the comparison result indicates thatthe output data Q[0:(N−1)] is less than the predetermined thresholdTHR[0:(N−1)], the comparator generates a logic low output, whichindicates that the FFs (i.e., second FF) handling the upper bits of theinput data Din may be safely disabled. At the rising edge of the clocksignal, the FF 545 would output the gating enable signal SGEn as toenable the clock gating circuit to gate the clock signal and/or thepower gating circuit to gate the supply voltage.

FIG. 6 is a flow diagram illustrating a method for a shift register toenter a low power mode according to some embodiments of the disclosure.The method may be implemented by any of the embodiments as describedabove. In step S601, current data stored in the shift register isloaded. The current data is referred to as the output data of FF(s). Forexample, the current data may be the output data Q[p] in the embodimentsof FIGS. 1 and 2 , the output data Q[(p−1):p] in the embodiments of FIG.4 , or the output data Q[0:(N−1)] in the embodiments of FIG. 5 . In stepS603, the current data is compared to a predetermined threshold. If thecurrent data is less than the predetermined threshold, the process goesto step S605 (i.e., “Yes” path). Otherwise, the process goes to “end”S607 and skips the step S605. In the step S603, the comparison may becomparison between one or more bits of the current data being stored inthe shift register. If the step S603 is true, the shift register entersa low power mode by disabling a portion of the FFs that handles theupper bits of the input data. The disabling of the portion of the FFsmay be performed by gating the clock signal and/or gating the supplypower. Accordingly, the portion of FF would be disabled for thesubsequent cycles and energy is conserved.

In accordance with some embodiments of the disclosure, a shift registerincludes a first flip-flop (FF), a second FF, and a gating circuit. Thefirst FF includes an input terminal coupled to a first portion of inputdata and an output terminal. The second FF includes an input terminalcoupled to a second portion of input data, an output terminal, a clockterminal coupled to a clock signal, a power terminal coupled to a supplypower. The second portion of the input data is subsequent to the firstportion of the input data. The gating circuit is coupled to the outputterminal of the first FF, and configured to disable the second FF forstoring the second portion of a subsequent input data according tooutput data currently being stored in the first FF.

In accordance with some embodiments of the disclosure, a shift registerincludes a first FF, a second FF, a third FF, and a gating circuit. Inthe embodiments, the first FF includes an input terminal coupled to afirst portion of input data and an output terminal. The second FFincludes an input terminal coupled to a second portion of input data, anoutput terminal, a clock terminal coupled to a clock signal, a powerterminal coupled to a supply power. The third FF is coupled between thefirst and second FFs. The third FF includes an input terminal coupled toa third portion of the input data and an output terminal. The thirdportion of the input data is between the first and second portions ofthe input data. The gating circuit is coupled to the output terminal ofthe third FF and configured to disable the second FF for storing thesecond portion of a subsequent input data according to output datacurrently being stored in the third FF.

In accordance with some embodiments of the disclosure, a method fordisabling flip-flop(s) (FF) in a shift register is provided. The methodincludes at least the following steps: loading current data stored in atleast one FF included in a shift register, comparing the current data toa predetermined threshold, and disabling a portion of the FFs in theshift register for handling upper bits of input data according to thecurrent data stored in at least one FF.

The embodiments of the disclosure may include any one or more of thenovel features described above, including in the Detailed Description,and/or shown in the drawings. As used herein, “at least one”, “one ormore”, “and/or”, and “coupled to” (or “couple to” are open-endedexpressions that are both conjunctive and disjunctive in operation. Forexample, each of the expressions “at least one of A,B and C”, “at leastone of A, B, or C”, “one or more of A, B, and C”, “one or more of A, B,or C” and “A, B, and/or C” means A alone, B alone, C alone, A and Btogether, A and C together, B and C together, or A, B and C together. Itis to be noted that the term “a” or “an” entity refers to one or more ofthat entity. As such, the terms “a” (or “an”), “one or more” and “atleast one” can be used interchangeably herein. In addition, theexpressions “A is coupled to B” or “A couple to B” may be referred to asA is directly or indirectly coupled to or connected to B.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A shift register, comprising: a first flip-flop(FF), including an input terminal coupled to a first portion of inputdata and an output terminal; a second FF, including an input terminalcoupled to a second portion of input data, an output terminal, a clockterminal coupled to a clock signal, a power terminal coupled to a supplypower, wherein the second portion of the input data is subsequent to thefirst portion of the input data; and a gating circuit, coupled to theoutput terminal of the first FF, and configured to disable the second FFfor storing the second portion of a subsequent input data according tooutput data currently being stored in the first FF.
 2. The shiftregister of claim 1, wherein the gating circuit comprises: a gating FF,including an input terminal coupled to the output terminal of the firstFF and an output terminal coupled to the second FF.
 3. The shiftregister of claim 2, wherein the gating circuit further comprises: alatch, including a first input terminal coupled to the output terminalof the first FF, second input terminal coupled to a reset signal, and anoutput terminal coupled to the input terminal of the gating FF.
 4. Theshift register of claim 2, wherein the gating circuit further comprises:a comparator, including a first input terminal coupled to the inputdata, a second input terminal coupled to a predetermined threshold, andan output terminal, and configured to compare input data to thepredetermined threshold, and output a comparison result at the outputterminal coupled the gating FF.
 5. The shift register of claim 2,further comprising an NOR gate coupled between the first FF and thegating circuit, wherein input terminals of NOR gate is coupled to atleast two of the first FFs.
 6. The shift register of claim 1, furthercomprising: a power gating circuit, including a first terminal coupledto the supply voltage, a second terminal coupled to the power terminalof the second FF, and a control terminal coupled to the gating circuit.7. The shift register of claim 1, further comprising: a clock gatingcircuit, including a first input terminal coupled to the clock signal, asecond input terminal coupled to the gating circuit, and an outputterminal coupled to the clock terminal of the second FF, and configuredto gate the clock signal from the second FF based on a gating enablesignal output by the gating circuit.
 8. The shift register of claim 1,wherein the first FF includes a plurality of first FFs for storing thefirst portion of the input data, and only the last first FF is coupledto be the gating circuit.
 9. The shift register of claim 8, wherein thesecond FF includes a plurality of second FFs for storing the secondportion of the input data.
 10. A shift register, comprising: a firstflip-flop (FF), including an input terminal coupled to a first portionof input data and an output terminal; a second FF, including an inputterminal coupled to a second portion of input data, an output terminal,a clock terminal coupled to a clock signal, a power terminal coupled toa supply power; a third FF, coupled between the first and second FFs,and including an input terminal coupled to a third portion of the inputdata and an output terminal, wherein the third portion of the input datais between the first and second portions of the input data; and a gatingcircuit, coupled to the output terminal of the third FF, and configuredto disable the second FF for storing the second portion of a subsequentinput data according to output data currently being stored in the thirdFF.
 11. The shift register of claim 10, wherein the third FF includes aplurality of third FFs.
 12. The shift register of claim 11, furtherincludes an NOR gate coupled between the plurality of third FFs and aninput terminal of the gating circuit.
 13. The shift register of claim10, wherein the gating circuit comprises: a gating FF, including aninput terminal coupled to the output terminal of the first FF and anoutput terminal coupled to the second FF.
 14. The shift register ofclaim 10, wherein the gating circuit further comprises: a latch,including a first input terminal coupled to the output terminal of thefirst FF, second input terminal coupled to a reset signal, and an outputterminal coupled to the input terminal of the gating FF.
 15. The shiftregister of claim 10, further comprising: a power gating circuit,including a first terminal coupled to the supply voltage, a secondterminal coupled to the power terminal of the second FF, and a controlterminal coupled to the gating circuit.
 16. The shift register of claim10, further comprising: a clock gating circuit, including a first inputterminal coupled to the clock signal, a second input terminal coupled tothe gating circuit, and an output terminal coupled to the clock terminalof the second FF, and configured to gate the clock signal from thesecond FF based on a gating enable signal output by the gating circuit.17. A method for disabling flip-flop(s) (FF) in a shift register,comprising: loading current data stored in at least one FF included in ashift register; comparing the current data to a predetermined threshold;disabling a portion of the FFs in the shift register for handling upperbits of input data according to the current data stored in the at leastone FF.
 18. The method of claim 17, wherein the portion of the FFs aresubsequent to the at least one FF for handling upper bits subsequent toa bit of input data handled by the at least one FF.
 19. The method ofclaim 17, wherein the disabling a portion of the FFs in the shiftregister comprises disabling the portion of the FFs in the shiftregister by gating a clock signal coupled to the portion of the FFs. 20.The method of claim 17, wherein the disabling a portion of the FFs inthe shift register comprises disabling the portion of the FFs in theshift register by blocking supply voltage provided to the portion of theFFs.